Why do I see timing failures within the Transceiver Subsystem FPGA IP when my variant has PTP enabled with “reconfig_group” settings in the project .qsf file? - Why do I see timing failures within the Transceiver Subsystem FPGA IP when my variant has PTP enabled with “reconfig_group” settings in the project .qsf file? Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.3, timing failures will be seen within the Transceiver Subsystem FPGA IP when PTP is enabled for the variant with “reconfig_group” settings in the project .qsf file. Resolution To work around this problem, create a quartus.ini file in your project directory that contains the following feature lines: vrfx2_gdr_quick_elab_rule_check_IPC_051=off vrfx2_gdr_quick_elab_rule_check_IPC_052=off dr_group_data=off This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16017685461 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 22.3 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']