GPIO default state before FPGA configuration (weak pull-up vs. pull-down) - GPIO default state before FPGA configuration (weak pull-up vs. pull-down) Between power-on and FPGA configuration, the GPIO pins are in a tristate condition with a weak pull-up enabled. As a result, the device’s digital outputs are initially driven HIGH and only switch to their intended state (LOW) after the FPGA configuration is complete. This behavior is causing problems for downstream signal evaluation. Questions: Is it possible to modify this default behavior of the GPIO pins before configuration? Specifically, can a pull-down (instead of a weak pull-up) be configured or enforced during the pre-configuration phase? Any guidance or recommended solutions would be appreciated. Replies: Re: GPIO default state before FPGA configuration (weak pull-up vs. pull-down) All good! Thank you very much for your support Replies: Re: GPIO default state before FPGA configuration (weak pull-up vs. pull-down) Do you have further question? Replies: Re: GPIO default state before FPGA configuration (weak pull-up vs. pull-down) Hello, The default pre-configuration weak pullup cannot be changed to a weak pulldown. This is because the hardware defaults are fixed and cannot be altered via software or fuse before configuration. If a low state is required prior to configuration, it is recommended to use external pulldown resistors to override the internal weak pullup. regards, Farabi Replies: Re: GPIO default state before FPGA configuration (weak pull-up vs. pull-down) Please review recent similar discussion Cyclone 10 LP I/O pins configuration