How can I control the logic cell insertion in VHDL designs when using Synopsys (Design Compiler or FPGA compiler) and the MAX PLUS® II software? - How can I control the logic cell insertion in VHDL designs when using Synopsys (Design Compiler or FPGA compiler) and the MAX PLUS® II software? Description You may need to inserting a logic cell for routing or reducing the fan-out of a signal. The flow is: Instanciate an logic cell component in your hardware description language (HDL) source code. Add the Synopsys directive set_dont_touch on the logic cell instance name. Add the MAX PLUS II software logic assignment STYLE=WYSIWYG on this logic cell. The following example ( ilf.vhd and ilc.scr ) describes how you can insert logic cell between a XOR gate and a flip-flop. Synopsys synthesizer (Design compiler or FPGA compiler) process ilc.vhd and ilc.scr to generate a MAX PLUS II EDIF file. This EDIF file contains the LCELL instanciation and the STYLE=WYSIWYG logic assignment. ---------------------------------------------------------- --- --- Insert an LCELL --- --- ilc.vhd --- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ilc IS PORT( dina, dinb, clk : IN STD_LOGIC; dout : OUT STD_LOGIC); END ilc; ARCHITECTURE a OF ilc IS signal foo_in,foo_out : std_logic; COMPONENT LCELL PORT ( a_in : IN STD_LOGIC; a_out: OUT STD_LOGIC); END COMPONENT; BEGIN U0 : LCELL port map (foo_in,foo_out); foo_in <= dina XOR dinb ; flip_flop: PROCESS(clk) BEGIN IF clk'event and (clk = '1') THEN dout <= foo_out; END IF ; END PROCESS ; END a; --- --- ------------------------------------------------------- /**********************************************************/ /* ilc.scr */ /* Synopsys script for design compiler or FPGA compiler */ /* */ read -f vhdl ilc.vhd set_dont_touch find(cell,{U0}) true set_attribute find(cell,{"U0"}) "LOGIC_OPTION" -type string "STYLE=WYSIWYG" compile write -f edif -hier -o ilc.edf Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']