DisplayPort HBR TX Native PHY Preset Not Aligned with Design Example - DisplayPort HBR TX Native PHY Preset Not Aligned with Design Example Description The DisplayPort TX Native PHY preset for HBR data rate is not aligned with the DisplayPort design example settings. The Native PHY preset configures the TX local clock division factor to 2, but in the design example settings, the expected clock division factor is 1. This issue causes the DisplayPort to transmit the serial data in the wrong clock rate. Resolution To work around this issue, change the Native PHY TX local clock division factor from 2 to 1. This issue is fixed in version 15.1 Update 2 of the DisplayPort IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 15.1.2 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25