Why does internal serial loopback test results fail when running the GTS JESD204B FPGA IP Design Example on Agilex™ 3 FPGA or Agilex™ 5 FPGA hardware? - Why does internal serial loopback test results fail when running the GTS JESD204B FPGA IP Design Example on Agilex™ 3 FPGA or Agilex™ 5 FPGA hardware? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may encounter a failed test result when running the internal serial loopback test with the GTS JESD204B FPGA IP Design Example. Resolution To work around this problem in the Quartus® Prime Pro Edition Software versions 25.3, download and install patch below. After installing the patch, do the following: In the GTS JESD204B IP GUI editor, IP > Main tab, enabled the following checkboxes: Enable PMA Avalon memory-mapped interface Enable control and status registers Depending on the data rate, configure the IP ➤ Analog Parameters ➤ Analog Rx ➤RX Adaptation mode: Manual: if data rate <= 7Gbps Auto: if data rate > 7Gbps Regenerate the design example. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15016860739 novalue ['Interfaces JESD204B (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3 ['Agilex™ 3 FPGAs and SoCs', 'Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']