Unsupported Signals in the Clocked Video Input II IP Core 14.1 - Unsupported Signals in the Clocked Video Input II IP Core 14.1 Description When you configure the Clocked Video Input II IP core, the vid_bit_width and vid_colour_encoding signals are not supported but visible to users. These signals do not affect the functionality of your design . Resolution Tie these signals to zero. This issue will be fixed in a future version of the Clocked Video Input II IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']