Why do my inferred memories have unexpected read-during write behavior when being implemented in Logic Cells? - Why do my inferred memories have unexpected read-during write behavior when being implemented in Logic Cells? Description Due to a problem in the Quartus® II software version 11.1 and later, memories that have been inferred from HDL code may have incorrect read-during-write behavior if they have been converted from RAM to logic cells. Memories may be converted if the Auto RAM to Logic Cell Conversion option is turned on. Resolution To avoid this problem, turn off the Auto RAM to Logic Cell Conversion option. Inferred RAMs may still be implemented in logic cells by setting the ramstyle synthesis attribute to logic . For more details on the ramstyle attribute, see the chapter Quartus II Integrated Synthesis in the Quartus II Handbook. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Arria® GX FPGA', 'Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® FPGAs', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V SX FPGA', 'Stratix® FPGAs', 'Stratix® GX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']