Why doesn't the Intel® Arria® 10 or the Intel Stratix® 10 DQ/DQS x4 configuration follow the pin-out placement documentation and the DQ/DQS Pins view in the Intel Quartus® Prime Pin Planner? - Why doesn't the Intel® Arria® 10 or the Intel Stratix® 10 DQ/DQS x4 configuration follow the pin-out placement documentation and the DQ/DQS Pins view in the Intel Quartus® Prime Pin Planner? Description When the EMIF IP is configured as DDR3 or DDR4 with x4 DQ/DQS groups, the Quartus® Prime may automatically assign DQ pins to pin locations that don't follow the x4 DQ/DQS groups defined in the device pin-out files. Resolution In the Intel® Arria® 10 or Intel Stratix® 10 I/O architecture for x4 DQ/DQS configuration, it is legal to assign a DQ pin to any DQ I/O location within a x12 I/O lane. Custom Fields values: ['novalue'] Troubleshooting FB: 445265; False ['External Memory Interfaces Arria® 10 FPGA IP', 'External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.0 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']