Why does in Intel® Quartus® Prime Pro Edition Software version 20.4, Intel Agilex® 7 DDR4 IP Traffic Generator 2.0 (TG2) Toolkit for the timeout or incorrect failure occur under the Configuration and Status Registers tab? - Why does in Intel® Quartus® Prime Pro Edition Software version 20.4, Intel Agilex® 7 DDR4 IP Traffic Generator 2.0 (TG2) Toolkit for the timeout or incorrect failure occur under the Configuration and Status Registers tab? Description When Traffic Generator 2.0 (TG2) Toolkit for the Intel Agilex® 7 DDR4 IP is configured such that TG_USER_WORM_EN = 1, TG_RETURN_TO_START_ADDR = 1, TG_ADDR_MODE = random or random-sequential, and TG_WRITE/READ_REPEAT_COUNT > 1, the Intel Agilex® 7 DDR4 IP Traffic Generator 2.0 (TG2) Toolkit failure signal will be incorrectly asserted. Resolution This problem is planned to be fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.4 onwards. Custom Fields values: ['novalue'] Troubleshooting 14012501674 False ['External Memory Interfaces (EMIF) IP'] ['FPGA Dev Tools Quartus® Prime Software'] 20.4 20.4 ['Agilex™ FPGA Portfolio'] ['novalue'] ['novalue'] ['novalue']