Error (175001): Could not place path required to route a signal from PLD core to the I/O pin - Error (175001): Could not place path required to route a signal from PLD core to the I/O pin Description You might see this error in the Quartus® II Software versions 13.0 and 13.1 when using Arria® V or Cyclone® V SoCs. This error occurs when you use Hard Processor System (HPS) I/O pins and instantiate an ALTLVDS Intel® FPGA IP in the FPGA design. This is not a valid error; there are no resource dependencies between the HPS I/O pins and the FPGA I/O pins. Resolution Download the following patch to fix this error for the Quartus II software version 13.1: Version 13.1 patch 0.15 for Windows (.exe) Version 13.1 patch 0.15 for Linux (.tar) Readme for the Quartus II software version 13.1 patch 0.15 (.txt) Custom Fields values: ['novalue'] Troubleshooting 2205971988 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 13.0 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']