Why does the "Generate Example Design" button not work when the Triple Speed Ethernet core is launched from the Qsys IP Catalog? - Why does the "Generate Example Design" button not work when the Triple Speed Ethernet core is launched from the Qsys IP Catalog? Description Due to a problem in the Quartus® Prime software, when the Triple Speed Ethernet core is added to a Qsys(Platform Designer) system from the Qsys IP Catalog, activating the "Generate Example Design" button in the IP parameter editor may cause the following Qsys error message to appear: "The example design cannot be generated when there are errors." The errors mentioned are system-level connectivity errors which are shown in the Qsys "messages" window. Resolution To work around this issue, generate the example design by invoking the Triple Speed Ethernet core IP parameter editor from the standalone Quartus IP Catalog. This problem is scheduled to be fixed in a future release of the Quartus Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 318367; True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 15.1 ['Arria® 10 FPGAs and SoCs', 'Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']