Serial Digital Interface Design Long Locking Time in 28nm Devices - Serial Digital Interface Design Long Locking Time in 28nm Devices Description The Serial Digital Interface (SDI) design has long locking time when switching from high definition (HD) to third-generation (3G) or when the core is reset after receiving 3G. The design takes a longer time to achieve frame lock when the rate detection block cannot detect the standard correctly because the data recovered during the rate detection is incorrect. This issue affects all SDI designs using 28nm devices. Resolution There is no workaround for this issue. This issue is fixed in version 12.1 SP1 of the SDI MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1.1 12.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']