Why does the Multi-Channel DMA Intel® FPGA IP for PCI Express Design Example targeting the Intel Agilex® 7 FPGA R-Tile devices fail in hardware testing when it is compiled with the Intel® Quartus® Prime Pro Edition Software version 22.4? - Why does the Multi-Channel DMA Intel® FPGA IP for PCI Express Design Example targeting the Intel Agilex® 7 FPGA R-Tile devices fail in hardware testing when it is compiled with the Intel® Quartus® Prime Pro Edition Software version 22.4? Description After programming the Multi-Channel DMA Intel® FPGA IP for PCI Express Design Example targetting the Intel Agilex® 7 FPGA R-Tile devices A0 or B0 die revision, the PIO tests will fail, and the DMA tests report queue reset failures. DK-DEV-AGI027RES : AGIB027R29A1E2VR0 = A0 die revision. DK-DEV-AGI027R1BES : AGIB027R29A1E2VR3 = B0 die revision. Resolution A patch is available to fix this problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 Regenerate and recompile the test design after installing the patch. Intel® Quartus® Prime Pro Edition Software v22.4 Patch 0.02 for Linux (.run) Intel® Quartus® Prime Pro Edition Software v22.4 Patch 0.02 for Windows (.exe) Readme for Intel® Quartus® Prime Pro Edition Software v22.4 Patch 0.02 (.txt) This problem was fixed in Intel® Quartus® Prime Pro Edition Software version 23.1 Custom Fields values: ['novalue'] Troubleshooting 14018629037 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['Agilex™ 7 FPGA I-Series Dev Kit']