How do I connect a differential pair from a Quartus® II-generated simulation netlist to another component that requires both the positive and the negative pins? - How do I connect a differential pair from a Quartus® II-generated simulation netlist to another component that requires both the positive and the negative pins? Description Quartus II-generated Verilog Output File ( .vo ) and VHDL Output File ( .vho ) netlists contain only the positive pins of differential pairs (e.g., LVDS and LVPECL). To connect a Quartus II-generated simulation netlist to another component that requires both the postive and negative pins, create a Verilog HDL or VHDL wrapper file around the netlist including a new output pin that inverts the positive output pin of the differential pair. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']