Is there a known issue with EPCS128 devices, when pausing the clock during an operation, and/or when operating at frequencies of 1MHz or less? - Is there a known issue with EPCS128 devices, when pausing the clock during an operation, and/or when operating at frequencies of 1MHz or less? Description Yes, there is a known low frequency marginality issue with EPCS128 devices manufactured before 2012, with a 65nm fabrication code. If a clock frequency of less than 1MHz is used and/or if the clock is paused for greater than 1us during an operation, the address that is loaded in the EPCS128 may not be the same as the address that was requested. This issue does not affect configuration of an FPGA from affected EPCS128 devices, since configuration operates at clock frequencies much greater than 1MHz. This issue may only be seen if accessing the EPCS128 during user mode. *If the process is 65nm, the fabrication code wiill be VS. Fixed devices have a Year Numeric (Y) of 2, whilst affected devices will have a Year Numeric (Y) < 2. Refer to PCN0805 http://www.altera.com/literature/pcn/pcn0805.pdf for further information on how to find these codes. Resolution To workaround this issue on an affected device, use a clock frequency > 1MHz and do not pause the clock for durations > 1us. The issue is fixed in devices with a date code of 2WW, where WW = work week. Related Articles Is it possible to use a very low frequency, variable frequency or intermittent clock for DCLK with EPCS or EPCQ configuration devices? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['Configuration Devices'] ['novalue']