Is there a known problem with Intel® Arria® 10 fPLL simulation when the clock switchover feature is enabled? - Is there a known problem with Intel® Arria® 10 fPLL simulation when the clock switchover feature is enabled? Description Due to a known problem in the Quartus® II software version 14.1 and earlier, you may see an incorrect output clock when simulating an Arria® 10 fPLL with the clock switchover feature enabled. Resolution This issue is scheduled to be fixed in a future release of the Quartus® II software. Custom Fields values: ['novalue'] Troubleshooting NA False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']