Why do I get timing violation associated with CK clock domain when implement multiple RLDRAM II interfaces sharing a single PLL and DLL? - Why do I get timing violation associated with CK clock domain when implement multiple RLDRAM II interfaces sharing a single PLL and DLL? Description When implementing multiple RLDRAM II interfaces sharing a single PLL and DLL on Stratix® III or Stratix IV in Quartus® II software version 11.1SP2, the CK/DK analysis may show false timing violations that should be cut. The false timing violations occur because each interface gives a different SDC clock name to the common clock buffer. Every new clock name results in a set of new timing paths, which are not covered by the existing false-path constraints. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']