RapidIO IP Core I/O Logical Layer Slave Module Provides Incorrect Read Response Data If Timeout Occurs During Response - RapidIO IP Core I/O Logical Layer Slave Module Provides Incorrect Read Response Data If Timeout Occurs During Response Description If a RapidIO IP core that includes an I/O Logical layer slave module responds to a read request and is in the process of sending read data when the Avalon-MM transaction times out, the part of the read data that was not yet sent is corrupted (set to zeroes). In addition, the RapidIO IP core might respond incorrectly to the next I/O slave command it receives on the I/O slave port. The IP core might erroneously flag this transaction as timed out, or might provide a smaller payload of read data than requested. The smaller payload in a read response might cause the original requestor to hang. Resolution This issue has no workaround. To minimize the chances of encountering this issue, you should set a high timeout value in the VALUE field of the Port Response Time-Out Control CSR at offset 0x124. This issue will be fixed in a future version of the RapidIO IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']