mapping SPI HPS Periphera over HPS. - mapping SPI HPS Periphera over HPS. I am using cyclone V, DE1 SOC (quartus lite 19.1), I am following this tutorial. I made changes to .qsys file of GHRD which i get from here for routing SPI over FPGA, every thing is good (no connection error, 0 error 0 warning) but when i try to generate .hdl it stops with some error. i just want to do SPI communication using python in HPS running linux. log Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper.sender Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper.sender Warning: hps_0.f2h_irq1: Cannot connect clock for irq_mapper_001.sender Warning: hps_0.f2h_irq1: Cannot connect reset for irq_mapper_001.sender Info: button_pio: Starting RTL generation for module 'soc_system_button_pio' Info: button_pio: Generation command is [exec /home/pratik/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /home/pratik/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /home/pratik/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /home/pratik/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/pratik/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/pratik/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_button_pio --dir=/tmp/alt8625_3109179678941513487.dir/0002_button_pio_gen/ --quartus_dir=/home/pratik/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt8625_3109179678941513487.dir/0002_button_pio_gen//soc_system_button_pio_component_configuration.pl --do_build_sim=0 ] Info: button_pio: Can't locate Getopt/Long.pm in @INC (you may need to install the Getopt::Long module) (@INC contains: /home/pratik/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa /home/pratik/intelFPGA_lite/19.1/quartus/sopc_builder/bin /home/pratik/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common /home/pratik/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio /tools/perl/5.28.1/linux64/lib/site_perl/5.28.1/x86_64-linux /tools/perl/5.28.1/linux64/lib/site_perl/5.28.1 /tools/perl/5.28.1/linux64/lib/5.28.1/x86_64-linux /tools/perl/5.28.1/linux64/lib/5.28.1) at /home/pratik/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl line 18. Info: button_pio: BEGIN failed--compilation aborted at /home/pratik/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl line 18. Info: button_pio: Done RTL generation for module 'soc_system_button_pio' Error: button_pio: Failed to find module soc_system_button_pio Info: button_pio: "soc_system" instantiated altera_avalon_pio "button_pio" Error: Generation stopped, 18 or more modules remaining Info: soc_system: Done "soc_system" with 17 modules, 1 files Error: qsys-generate failed with exit code 1: 2 Errors, 4 Warnings Info: Finished: Create HDL design files for synthesis Replies: Re: mapping SPI HPS Periphera over HPS. Thankyou for your help.. i am able to solve my problem.. Replies: Re: mapping SPI HPS Periphera over HPS. Hi, Are you still facing this issue? Have you check if your directory of your Quartus design files is in the right directory? After downloading the GSRD, I recommend that you have your files inside the GSRD directory(Quartus design files).