What types of VHDL wait constructs does Quartus II synthesis support? - What types of VHDL wait constructs does Quartus II synthesis support? Description The Quartus® II software supports only a single VHDL wait-until statement in a process. Other VHDL wait constructs such as wait-for statements, or processes with more than one wait statement, are not synthesizable. For example, Quartus II integrated synthesis supports the following wait-until syntax: architecture dff_arch of ls_dff is begin output: process begin wait until (CLK'event and CLK='1'); Q <= D; Qbar <= not D; end process output; end dff_arch; The software does not support the following types of wait statements, and generates an error during synthesis: process --Unsupported process declaration begin CLK <= ‘0’; wait for 20 ns; CLK <= ‘1’; wait for 12 ns; end process; output: process begin --Unsupported process declaration wait until (CLK'event and CLK='1'); Q <= D; Qbar <= not D; wait until (CLK'event and CLK='0'); Q <= 0; Qbar <= 1; end process output; Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']