Why are tx_reset_ack and rx_reset_ack signals not going high in my dual simplex design? - Why are tx_reset_ack and rx_reset_ack signals not going high in my dual simplex design? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and earlier, you will observe a problem where the tx_reset_ack and rx_reset_ack signals do not go high when you enable the Avalon® memory-mapped interface only for TX Simplex IP or only for RX Simplex IP in your Dual Simplex design. Resolution To work around this problem, you need to enable the Avalon memory-mapped interface for both TX and RX Simplex IP. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Errata 16027686647 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']