Why does the Altera PLL IP signal phase_done not assert in gate-level simulation of dynamic phase shift? - Why does the Altera PLL IP signal phase_done not assert in gate-level simulation of dynamic phase shift? Description Due to a problem in the Quartus® II software version 15.0.2 and earlier, phase_done may not assert after a phase shift by phase_en pulse in the gate-level simulation of dynamic phase shift with Altera PLL IP. This problem affects simulation only. Resolution This problem is fixed in the Intel® Quartus® Prime Standard Software version 16.0 Related Articles Why is my Cyclone® V or Stratix® V Altera_PLL reset port is inverted in simulation? Custom Fields values: ['novalue'] Troubleshooting 1408194994 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 16.0 14.1.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']