Can the transceiver PHY in Gigabit Ethernet mode compensate for clock frequency differences between the recovered clock and the reference clock during 1000BASE-X/SGMII auto-negotiation? - Can the transceiver PHY in Gigabit Ethernet mode compensate for clock frequency differences between the recovered clock and the reference clock during 1000BASE-X/SGMII auto-negotiation? Description No, the transceiver PHY (ALT2GXB, ALT_GXB and Native PHY IP's) in Gigabit Ethernet mode cannot compensate for clock frequency differences between the recovered clock and the reference clock during 1000BASE-X/SGMII auto-negotiation. The Rate Match FIFO in the transceiver PHY is capable of inserting or deleting the first two bytes of /C2/ ordered sets during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered sets could cause the 1000BASE-X/SGMII PCS state machine to function incorrectly. Resolution Refer to Application Note AN 537 Implementing UNH-IOL Test Suite Compliance in Arria® GX and Stratix® II GX Gigabit Ethernet Designs (PDF) . This application note can be applied to all device families. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue No plan to fix ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® GX FPGA', 'Stratix® II GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']