External Memory Interfaces in Agilex™ FPGAs (Part 3): Verification - Same Course in Chinese: Altera® Agilex™ 器件中的存储器接口验证 Same Course in Japanese: インテル Agilex™ デバイスのメモリー・インターフェイスの検証 34 Minutes This training is part 3 of 4. The Altera® Agilex™ family of FPGAs introduce brand new, higher performance architectures for implementing external memory interfaces, including DDR5 running at up to 5.6 Gbps on some devices. This part of the training discusses how to perform a simulation of the memory interface IP using a generated example design. When generated, the IP creates all the files needed to perform a simulation. Timing analysis of the IP is also discussed along with suggestions for timing closure. The hard resources used for the external memory interfaces IP along with easier-to-read timing reports simplify analysis and closure. Course Objectives At course completion, you will be able to: Verify the functionality of an Altera® Agilex™ FPGA EMIF design through simulation Perform a timing analysis of both the core logic and I/O periphery for a memory interface Know what optimizations to enable to close timing, if necessary Skills Required Background in digital logic design Basic knowledge of memory interfaces and their implementation in Altera® FPGA devices Familiarity with the Altera® Quartus® Prime software If the audio for the course does not start automatically, press pause and then play on the course player. A transcript of the course audio is available in the Notes or closed captioning (cc) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code : FPGA_OAGMEM103. FPGA_OAGMEM103. <p>External Memory Interfaces in Agilex FPGAs (Part 3): Verification</p>