Why am I not able to place more than two independent ALTLVDS interfaces in one I/O sub-bank in Intel® Arria® V devices? - Why am I not able to place more than two independent ALTLVDS interfaces in one I/O sub-bank in Intel® Arria® V devices? Description Intel® Arria® V devices support up to two independent ALTLVDS interfaces in each sub-bank. So, for example, you can place two ALTLVDS interfaces in bank 8A driven by two different PLLs, provided the LVDS channels are not interleaved. If you violate this limitation, you will receive an error message during project compilation. Resolution The condition is listed in the "Arria® V Device Handbook Volume 1: Device Interfaces and Integration", "True LVDS Buffers in Arria® V Devices" part. Custom Fields values: ['novalue'] Troubleshooting N/A False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']