Higher Delays and Skews Expected for UniPHY External Memory Interfaces Corner I/Os in Stratix V Devices - Higher Delays and Skews Expected for UniPHY External Memory Interfaces Corner I/Os in Stratix V Devices Description In Stratix V devices, the corner I/O banks are expected to have higher core-to-I/O and I/O-to-core delay and skew values than the other I/O banks, and are unsuitable for interfacing with external memory at frequencies above 667 MHz.The characteristics of the corner I/O banks are not yet reflected in the Stratix V timing models available in version 10.1 of the Quartus II software; consequently, timing analysis will not accurately characterize the performance of the corner I/Os. Resolution Avoid using the outer I/O banks at the upper and lower sides of the device. Custom Fields values: ['novalue'] Troubleshooting novalue True ['I O'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']