Why are the Output Enable/Disable Times for a bus the minimum value for all bits of the bus？ - Why are the Output Enable/Disable Times for a bus the minimum value for all bits of the bus？ Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1, the Output Enable/Disable Times reports the minimum delays instead of displaying the maximum value for bus bits. This problem occurs when targeting Intel® Stratix® 10 devices. Resolution To work around this problem, expand the aggregated data bus bits and identify the maximum delay value manually. This problem was fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1507225795 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']