Why does the DisplayPort Intel® FPGA IP design example fail to generate a programming file when using the Intel® Quartus® Prime Pro Edition Software v19.1? - Why does the DisplayPort Intel® FPGA IP design example fail to generate a programming file when using the Intel® Quartus® Prime Pro Edition Software v19.1? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v19.1, designs that use the Nios® II/e processor core without a valid Nios® II processor license will fail to generate programming files even though the design compilation is successful. The DisplayPort Intel® FPGA IP design example uses the Nios II/e processor core. Hence, it will be impacted by this problem. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software v19.1, install the following patch and regenerate the DisplayPort Intel® FPGA IP design example: Version 19.1 patch 0.02 for Windows (.exe) Version 19.1 patch 0.02 for Linux (.run) Readme for the Intel ® Quartus® Prime Pro Edition Software v19.1 patch 0.02 (.txt) This problem is fixed starting with the Intel Quartus Prime Pro Edition Software v19.2. Custom Fields values: ['novalue'] Troubleshooting 1507134253 False ['DisplayPort'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.2 19.1 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']