What are the correct register settings for transceiver reconfiguration controller tap 5 offset of dfe_offset register for Stratix® V and Arria® V FPGAs? - What are the correct register settings for transceiver reconfiguration controller tap 5 offset of dfe_offset register for Stratix® V and Arria® V FPGAs? Description The Transceiver Reconfiguration Controller DFE registers information for address 0x1B (dfe_offset), offest 0x5 (tap 5) is not correct in the V-Series Transceiver PHY IP Core User Guide . Resolution The correct settings for tap 5 coefficients and polarity are as follows: Offset Bits R/W Register Name Description 0x5 [2] RW tap 5 polarity Specifies the polarity of the fifth post tap as follows: 0: negative polarity 1: positive polarity [1:0] RW tap 5 Specifies the coefficient for the fifth post tap. The valid range is 0–3. The V-Series Transceiver PHY IP Core User Guide is scheduled to be updated in a future release. Custom Fields values: ['novalue'] Troubleshooting 15011506554 False ['novalue'] ['novalue'] novalue novalue ['Arria® V FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']