Cyclone® V, Arria® V and Arria®10: SoC Hardware Overview - Same Course in Japanese: SoC ハードウエア概要パート１ 42 Minutes In this training you will learn about Hard Processor Subsystem (HPS) in the Cyclone® V, Arria® V, and Arria® 10 SoCs. The online training includes information about the MPU subsystem, including the Arm Cortex-A9 processor core, flash controller, interconnect and debug capabilities. Various components of the MPU subsystem such as the processor, co-processors, interrupt controller, and caches will be discussed. Course Objectives At course completion, you will be able to: Understand the Hard Processor System Arm Cortex-A9 processor Cores as implemented in Altera® SoCs Know the peripherals and architecture to design with Cyclone V and Arria 10 SoC. Skills Required Basic knowledge of FPGA architecture Embedded Systems If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OEMB5500. FPGA_OEMB5500. <p>Cyclone V, Arria V and Arria10: SoC Hardware Overview</p>