Arria V and Cyclone V Hard Memory Controller Options May Not Function Correctly for Interfaces with 2 Chip Selects - Arria V and Cyclone V Hard Memory Controller Options May Not Function Correctly for Interfaces with 2 Chip Selects Description This problem affects DDR2 and DDR3, LPDDR2, QDR II, and RLDRAM II products. On Arria V and Cyclone V devices, hard memory controller options for user refresh, self refresh, or deep power-down may not function correctly for interfaces with two chip selects. This problem may cause simulation to hang, and in some cases may result in hardware failure. Resolution The workaround for this issue is to edit the RTL file altera_mem_if_hard_memory_controller_top_arriav.sv (for Arria V designs) or altera_mem_if_hard_memory_controller_top_cyclonev.sv (for Cyclone V designs), and change the following lines: .localrefreshchip ( local_refresh_chip ), .localdeeppowerdnreq ( local_deep_powerdn_req ), .localdeeppowerdnchip ( local_deep_powerdn_chip ), .localselfrfshreq ( local_self_rfsh_req ), .localselfrfshchip ( local_self_rfsh_chip ), � to: .localrefreshchip ( local_refresh_chip_wire ), .localdeeppowerdnreq ( local_deep_powerdn_req ), .localdeeppowerdnchip ( local_deep_powerdn_chip_wire ), .localselfrfshreq ( local_self_rfsh_req ), .localselfrfshchip ( local_self_rfsh_chip_wire ), � This issue will be fixed in a future version. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']