Why do I see small hold time violations in the "H-tile Hard IP for Ethernet Intel® FPGA IP"? - Why do I see small hold time violations in the "H-tile Hard IP for Ethernet Intel® FPGA IP"? Description Due to a problem in the Intel® Quartus® Pro Software version 18.0 and earlier, you might see small hold time violations in the "H-tile Hard IP for Ethernet Intel® FPGA IP." Resolution To work around this problem, try another fitter seed to avoid these timing violations. This problem is fixed in Intel® Quartus® Prime Pro Edition Software version 18.1. Custom Fields values: ['novalue'] Troubleshooting FB: 553603; True ['Ethernet', 'Low Latency 100G Ethernet IP for Arria® 10 and Stratix® V'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue'] - 2023-01-23