NativeLink Simulation for UniPHY External Memory Interfaces fails for VHDL Output - NativeLink Simulation for UniPHY External Memory Interfaces fails for VHDL Output Description When you specify VHDL output for the DDR2 and DDR3 SDRAM Controller with UniPHY, the QDR II and QDR II SRAM Controller with UniPHY, or the RLDRAM II Controller with UniPHY, and attempt to simulate using NativeLink, NativeLink fails and reports that it cannot find the file < design_name > .vho in the top-level directory. Resolution The workaround for this issue is to not use NativeLink for simulations of VHDL designs, but to set up simulation manually instead. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']