Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa - Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4. I followed the procedure to generate a test design using Quartus Prime Pro, and I changed the working directory to the design/pcie_design_tb/pcie_design_tb/sim/mentor/ However on page 16 where it says I should invoke vsim which it said brings up a console where I can run the following commands, which it lists as do msim_setup.tcl then ld_debug and run -all However when I invoke vsim, it expects me to put in the testbench design. Without this it complains that "No Design Loaded!" and it wont run. Or I will try the ld_debug and run -all it will try to compile with over 2500 warnings and one fatal error saying no design loaded. Not sure if this is an error in the user guide. The transcript window is used to input paramaters, not by invoking vsim. I'm using the DMA design. Can someone assist me step by step on how I can sucessfully compile this design? Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Thanks for the sharing of your conclusion and findings. You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix. Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Solved! But there are some points I want addressed. So everything worked in CentOS (10.0). I compiled the design for the PCI Express 3.0 x8 using the standard MM option, the generated design example did compile but it ended up failing because there was no stimulus, so it ran until 4 seconds and quit. (took 8 hours to complete) I then ran the other option, the PCI Express 3.0 x 16 (MM+) which automatically downtrains to x8, in the IP Generation dialogue box it does give you the option to have Intel BFM to apply, so I did that, compiled in QuestaSim and it ran to completion, everything worked. So why doesn't the User Manual explain if you run the standard x8 option that you have to supply your own testbench stimulus? And why doesn't the IP editor allow you to apply the Intel BFM for just the x8 option? In regards to switching to CentOS and disregarding my Windows problem, I feel like Quartus should be able to recognize spaces between names in the user path, and all this confusion could have been resolved and I could have proceeded with the Windows environment. The space between "Valued Customer" in my user downloaded configuration path that Quartus used DID created problems. I made sure to avoid any spaces during my CentOS installation and used short paths. Thanks for all the help and I hope this helps others out. Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Sorry for the delay. The problem was with my Windows install, it has a space in a directory that has all my config data for all my programs. I ported the design over to CentOS 10, the latest update. It compiled in QuestaSim, took over 8 hours to simulate then failed. I used the design you sent me. I could not see any simulation waveforms. Will try again. If you don't mind, can you please append the WLF data? Once your simulation succeeds, it should post a message and ending the simulation run. I'm interested in the waveform data which you can save from the File menu. I can at least load this data in the advent there is another failure. Thank you Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Hi, I finally find a way to upload the generated project. Please extract below files individually: s10_ed.zip.zip --> s10_ed.zip s10_ed.z01.zip --> s10_ed.z01 s10_ed.z02.zip --> s10_ed.z02 s10_ed.z03.zip --> s10_ed.z03 s10_ed.z04.zip --> s10_ed.z04 Put s10_ed.zip, s10_ed.z01, s10_ed.z02, s10_ed.z03, s10_ed.z04 into the same directory(e.g. ss) then extract s10_ed.zip to another directory(e.g. ../st). All .z0X files will be merged into one file called pcie_s10_hip_avmm_bridge_0_example_design_gen3x8dma_original.zip. Hope this helps. Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Sure. I'm using Q23.4.0 Pro. Extract the .zip to get .ip Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Can you kinly provide your .IP variation file used to simulate the PCI Express core? And what version of Quartus Pro are you using? Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Sorry I can't use those external links. Due to the limitation of forum, my suggestion is to contact your local DFAE. They could help check your system on-site and provide corresponding supports. Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa I updated my simulator from the ModelSim Starter Ed and Questa Starter to Siemens Questa, Questa Intel FPGA Ed-64 2024.3 and ran all the previous commands as outlined in the User Guide and I am still getting the "failed to load design" after generating 3000+ errors as previously I got. This leads me to believe there is something I'm not checking in the IP variant checkboxes. I contend, everything was followed according to the User Guide. Can you please upload your complete folder including the IP variant for my device you generated and upload it to FileTransfer.io or SendGB, which is a free hosting site for files up to 5GB ? Once I receive this, and find out where my errors orginiated from and after sucessful simulation, I'll mark this as Solved and explain what I did wrong. Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa The User Guide specifically mentions "No license is required", therefore it is free of cost to simulate including using the starter ed. --On 7/17 we have aligned to AVMM PCIe IP, you're now discussing AVMM+ PCIe IP? My discussion with you so far is all based on the sim of AVMM PCIe IP. --"No license requirement" in AVMM+ PCIe UG means this IP is free to use, and you can compile the design to get sof. Doesn't mean the Questa starter edition can handle such complicated simulation. Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa I think I'm narrowing down what the problem is. First I wanted to correct you, you stipulated "--Please not using starter version" The User Guide specifically mentions "No license is required", therefore it is free of cost to simulate including using the starter ed. Here is what I think the problem is. The top level design module is outside the directory structure that the manual says to change into. In my design, when I go to C:\intelFPGA_pro\23.3\avmm_bridge_512_0_example_design\pcie_ed_tb\pcie_ed_tb\sim the top level module is there, called pcie_ed_tb.v This file is nowhere else in the file structure except there. So when I change to the testbench directory C:\intelFPGA_pro\23.3\avmm_bridge_512_0_example_design\pcie_ed_tb\pcie_ed_tb\sim\mentor and type in do msim_setup.tcl it seems to not notice this top level module, I can't find this file anywhere in the Library window. Can you confirm? So by doing ld_debug at this point is going to be fatal error if it can't load the top level module. I even put the top level module in the testbench directory and it still won't load it. Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa I'm not able to upload an example for you to try because the zipped file is still too large. Splitting zip files can't be uploaded. Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa # ** Error (suppressible): (vopt-14408) Intel Starter FPGA Edition recommended capacity is 5000 non-OEM instances. There are 9399 non OEM instances. Expect performance to be severely impacted. --Please not using starter version I typed vsim in Questa or ModelSim... --vsim is the command to launch Questa, not the command used inside Questa That being said, I clicked on pci_ed_tb after typing vsim as the testbench file --do vsim at pcie_ed_tb/pcie_ed_tb/sim/mentor Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa can you also clarify, After you changed into the testbench subdirectory, you typed in vsim, this brings up a window which expects you to put in the top level testbench to simulate. You don't mention any designs, you say you type vsim, then do msim_setup.tcl, then ld_debug and run -all. I typed vsim in Questa or ModelSim, it just expects you to load the top level design. That being said, I clicked on pci_ed_tb after typing vsim as the testbench file, but still couldn't load the design. Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Hi, I've done everything you've told me, followed the directions in the user guide, and unfortunately it is not compiling or loading the design. Nothing I do works. Can I please have this case elevated and have another support person and fresh eyes to evaluate the issue? For reference, I have a Windows 11 computer and running designs on Questa Intel Starter Edition 2032.2. Generated design was used on Quartus Pro 23.3. I believe you ran simulation on Linux. I've tried now simulating the Gen3 x 16 lane IP core, per the instructions in the L-Tile and H-Tile Avalon MM + Intel FPGA IP for PCI Express User Guide on pp. 12-16. I've selected the right core (MM+) on the toolbar to generate my IP variant and selected the options as listed on p. 14 of the User Guide. My specific FPGA is 1SX280HU2F50E1VG Sucessfully generated the design example. Open up Questa, change to this directory C:\intelFPGA_pro\23.3\avmm_bridge_512_0_example_design\pcie_ed_tb\pcie_ed_tb\sim\mentor I run do msim_setup.tcl Then I run ld_debug I have over 3500 warnings and finally "failed to load design." I've attached the complete transcript run. It does NOT work on a Windows 11 computer. I am assuming this is a mapping error. Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Once you have project generated, continue doing synthesis & simulation. Do not use "Clean Project". I found this function cleans several sim directories which cannot be recovered. Your library mapping issue probably because of this. Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa I tried on linux using 1SX280HU2F50E 2 VG and Questa worked fine. The sim took a while to complete. After synthesis, I went to pcie_ed_tb/pcie_ed_tb/sim/mentor, typed vsim there, then did "do msim_setup.tcl", "ld_debug" and "run -all" inside Questa. If you check msim_setup.tcl, the QSYS_SIMDIR ./../ should point to the directory of pcie_ed_tb.v and common. I suggest you do the same thing with me. Go to pcie_ed_tb/pcie_ed_tb/sim/mentor and type vsim to start Questa there. Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa I believe I found the issue, but I still need to fix this. So I've done all steps above and as correctly done per the User Guide on p. 19-21. Again, it claims "Error loading design" Opening Questa and changing directory to the testbench directy and under sim for mentor, I type in do msim_setup.tcl, it maps all my libraries to the files and modules of the testbench directory. I noticed there is apparently a Library Mapping Mismatch. The project window list various files that don't map to the location of the file in my project location on my host drive. But when I click Edit, it seems to find it. Double clicking it though says module isn't defined and couldn't load it. There needs to a be a 1-to-1 mapping of these files as listed in the Library window. So the issue is the msim_setup.tcl needs to correctly map the location of my design files on my host drive. I'm not familir with .tcl files. To assist in arriving at a solution, This is the location of my design file C:\intelFPGA_pro\23.3\pcie_s10_hip_avmm_bridge_0_example_design and here is the simulation directory C:\intelFPGA_pro\23.3\pcie_s10_hip_avmm_bridge_0_example_design\pcie_ed_tb\pcie_ed_tb\sim\mentor Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa I did the Analysis and Synthesis as recommended, and the design still does not compile. The generated design does say it generated sucessfully. Upon invoking vsim and running do msim_setup.tcl and ld_debug the last message says "Error loading design". Doesn't explain what file it can't locate or find. I've followed all instructions on p. 19-21 and still fails. I was able to suppress other past errors as the paths to the design filed was over the 128 character limit on Windows, by changing Windows environment variable LongPathsEnabled to "1". [HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem] LongPathsEnabled=1 Can you please confirm on your end by generating the design example for my device, 1SX280HU2F50E1VG, and using Questa it works? Not sure why it's not loading the design? Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Complete "Analysis & Synthesis" before you do simulation. Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Open your generated example design and run "Analysis & Synthesis". After this is done, go to pcie_ed_tb/pcie_ed_tb/sim/mentor and do "vsim" etc described at page 21 in user guide. Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa I got rid of the spaces, and again tried compiling the design in Questa. It has output a new error message and stops. # ** Error: (vlog-7) Failed to open design unit file "../../../../ip/pcie_ed/pcie_ed_DUT/altera_pcie_s10_hip_avmm_bridge_2223/sim/pcie_ed_DUT_altera_pcie_s10_hip_avmm_bridge_altera_xcvr_pcie_hip_native_s10_2223_bbreury.v" in read mode. # No such file or directory. (errno = ENOENT) Since Intel has now obsolete static design examples, is there a legacy model that you can upload that I can use to simulate? I believe the problem exists when I don't have a Intel FPGA Board, but the Terasic Apollo S10 SOM which means I have to put no board design but otherwise put my chipset in and have a dynamic configuration and thats the problem. Can you try and put my chipset in an try to dynamically generate a design example and simulate it with no errors? 1SX280HU2F50E1VG Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa It looks like the failure happens during example design generation. Line 358 of the text file shows your project path has a space, please fix this first then regenerate example design. As p.19 says, turn on the Simulation and Synthesis options, for DMA design please Enable Avalon-MM DMA. Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Hi, I'm using the L-tile and H-tile Avalon® Memorymapped Intel® FPGA IP for PCI Express So I've set it to Gen3x8, 256 bit 250 MHz DMA I've set all parameters according to the User Guide on p. 19, this is for Quartus Prime Suite 21.1 I previously included the error file, which stops at the error saying it can't find aldec/altera_pcie_s10_64avmm_adapter/altera_pcie_s10_adapter.v Then says failed to generate design example. Despite the error, I try to simulate in Questa by changing the working directory to the design example, it won't load the design. Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Hi, I'd like to confirm with you which IP you're using. AVMM or AVMM+ for PCIe? I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. --AVMM+ PCIe only provides Gen3x16 512 bit 250 MHz, not selectable; DMA is the only example, not changeable After I hit Generate Design Example with my specific IP patters as Gen3 x 8, 250 Mhz, DMA enabled, Simulation only --AVMM PCIe can select to this setting, Gen 3x8 256 bit 250 MHz DMA Regards, Rong Replies: Re: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa Wanted to give an update. After I hit Generate Design Example with my specific IP patters as Gen3 x 8, 250 Mhz, DMA enabled, Simulation only, and I have applied these settings to the Intel Stratix 10 GX FPGA Development Kit DK-DEV-1SGX-H-A under Board settings, the design fails to generate the example. The output from the IP editor window is in the attached file. I've also kept the same settings to another board I have I bought from Terasic, the Apollo S10 SOM, which has a similar chipset as the above but isn't listed under the Boards, so I click "None" and generate design, and it still fails to provide a simulation model. Can anyone explain this or provide me with a simulation model, as long as it's Gen3x8, I don't mind ? Or tell me whats going wrong here? All simulation options are correctly followed in the User Guide. Does anyone else have this issue ? - 2025-07-15