Max10M16DCU324 FPGA data and clock - Max10M16DCU324 FPGA data and clock I used Max10M16DCU324 to read adc data from adc driver. 1) ads4222, 50MHz, 12 bit parallel. 2) I connect 2 x 12 bit data to bank 4 IO, but I connect the data strobe clock at bank 3. Is there any problem for it? Is it must to keep data + clock in the same bank? Replies: Re: Max10M16DCU324 FPGA data and clock Hi User Since we don't receive any feedback to the thread, we will transition the thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Eng Wei Replies: Re: Max10M16DCU324 FPGA data and clock Hi there We don't expect to see Quartus tools flagging error on this, unless you see otherwise. On the other hand, you can consider to apply source synchronous mode below for your implementation: https://www.intel.com/content/www/us/en/programmable/documentation/mcn1395213337540.html#mcn1395754852395 You can also consider to enable I/O Elements for your data path. thanks. Eng Wei