RapidIO II IP Core Might Declare Loss of Scrambler Synchronization If Link Partner Has Different Reference Clock Source - RapidIO II IP Core Might Declare Loss of Scrambler Synchronization If Link Partner Has Different Reference Clock Source Description If the RapidIO II IP core and its RapidIO link partner have independent reference clock sources, the RapidIO II IP core declares a scrambler synchronization error by setting bit [14] of the Port 0 Error Detect CSR at offset 0x340, around the time of the first clock compensation sequence. Resolution This issue has no workaround. This issue is fixed in version 13.1 Update 2 of the RapidIO II MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1.2 13.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']