Why is there an intermittent link-up issue after changing the loopback mode of the F-Tile Serial Lite IV Intel® FPGA IP system console design example? - Why is there an intermittent link-up issue after changing the loopback mode of the F-Tile Serial Lite IV Intel® FPGA IP system console design example? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, you may see the intermittent link-up issue after changing the loopback mode on the F-Tile Serial Lite IV Intel® FPGA IP System Console design example when running at 1Gbps datarate. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, generate the F-Tile Serial Lite IV Hardware Test Design Example and insert "after 10000" at line 225 in the ed_hwtest/system_console/sliv_ftile.tcl file. Example sliv_ftile.tcl after fix on Line 224 to 226: ... sys_reset after 10000 } ... This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.3. Custom Fields values: ['novalue'] Errata 15011321156 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue'] - 2023-01-10