What is the behavior of the traffic generator status signals in the Intel® Arria® 10 and the Intel® Stratix® 10 EMIF IP example design? - What is the behavior of the traffic generator status signals in the Intel® Arria® 10 and the Intel® Stratix® 10 EMIF IP example design? Description The traffic_gen_pass signal will go high if there are no bit errors and the test loops for a specific number of cycles. In the infinite loop test mode, the traffic_gen_pass signal will never go high. The traffic_gen_fail signal goes high whenever a pnf_per_bit (pnf = pass not fail) signal goes low, regardless of how many loops the test runs. The traffic_gen_timeout signal goes high when there is a timeout due to a problem with the traffic generator. Resolution All traffic generator status signals will remain low if the interface fails calibration. Custom Fields values: ['novalue'] Troubleshooting FB: 365354; False ['External Memory Interfaces Arria® 10 FPGA IP', 'External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.0 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']