Why do Ethernet links fail when using the Ethernet Subsystem Intel® FPGA IP on the Intel Agilex® 7 F-tile FHT ports at different rates? - Why do Ethernet links fail when using the Ethernet Subsystem Intel® FPGA IP on the Intel Agilex® 7 F-tile FHT ports at different rates? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, Ethernet links will fail the Intel Agilex® 7 F-tile FHT ports when the FHT ports are operating at different data rates within the Ethernet Subsystem Intel® FPGA IP. Resolution There is no workaround for this problem. This problem was fixed in version 23.3 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16019233416 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']