Why does my Intel® P-Tile Avalon®-ST for PCI Express* IP RX interface behave differently depending on the reset condition? - Why does my Intel® P-Tile Avalon®-ST for PCI Express* IP RX interface behave differently depending on the reset condition? Description The Intel® P-Tile Avalon®-ST for PCI Express* IP implements a deskew module in the FPGA fabric to realign receive side packets coming from Embedded Multi-die Interconnect Bridge (EMIB) interface. The deskew module has a reset problem that could cause misalignment on the Avalon-ST RX interface. Resolution This problem is fixed in the Intel® Quartus® Prime Pro Edition software version 20.1. Custom Fields values: ['novalue'] Troubleshooting 14010307524 False ['Avalon-ST Stratix® 10 Hard IP for PCI Express', 'PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.3 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']