Why do I get a mismatch between expected decoder output vs actual decoder output when simulating the 5G-LDPC IP Core with Aldec Riviera-Pro version 2020.04? - Why do I get a mismatch between expected decoder output vs actual decoder output when simulating the 5G-LDPC IP Core with Aldec Riviera-Pro version 2020.04? Description If the 5G LDPC Intel® FPGA IP design example is generated using the Intel® Quartus® Prime Pro Edition Software version 21.1 or 21.2, you will see the decoder expected outputs do not match the actual outputs in Aldec Riviera-Pro simulation. This problem was root caused in the Aldec Riviera-Pro version 2020.04, which the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2 generates simulation files for. Resolution This problem has been resolved in Aldec Riviera-PRO version 2021.4, which is supported in the Intel® Quartus® Prime Pro Edition Software version 21.3 onwards. Regenerate your design with the updated Intel Quartus software version. Custom Fields values: ['novalue'] Troubleshooting 22012465379 False ['5G LDPC'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.2 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']