Is rx_syncclock available for the Soft LVDS Intel® FPGA IP receiver with an even SERDES factor? - Is rx_syncclock available for the Soft LVDS Intel® FPGA IP receiver with an even SERDES factor? Description The rx_syncclock is unused when the Intel® MAX® 10 FPGA Soft LVDS has an even serializer/ deserializer (SERDES) factor. Therefore, rx_syncclock is not available in the Soft LVDS Intel® FPGA IP receiver when an even SERDES factor is selected. Resolution No workaround is needed for this problem. Custom Fields values: ['novalue'] Troubleshooting FB: 466147; HSD: 2205874987 False ['Soft LVDS IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.0 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']