* ns: ERROR: <variant>_test_bench/i_readdata is 'x' - * ns: ERROR: <variant>_test_bench/i_readdata is 'x' Description Due to problem in the Quartus® II software version 12.0sp2 and later, you may face this issue on simulation if your Qsys design has NiosII and SDRAM controller, and reset vector is assigned to the SRAM controller. This is caused by the external simulation model, " altera_sdram_partner_module.v " which generated by Qsys, the output returns read data 1 cycle earlier than CAS latency parameter, read data for NiosII also becomes unknown 'x'. Resolution To work around this issue, use the memory model provided by memory device vendor or add one more cycle to output port for read data like below. [altera_sdram_partner_module.v] //Original // assign zs_dq = read_valid ? read_temp : {32{1\'bz}}; //Workaround assign zs_dq = read_valid_reg ? read_temp_reg : {32{1\'bz}}; always @(posedge clk) begin read_temp_reg <= read_temp; read_valid_reg <= read_valid; end This issue is scheduled to be fixed in a future release of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0.2 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']