Why can’t the Agilex® 5 FPGA E‑Series 065B Modular Development Kit be configured using the configuration file generated from the GTS AXI Streaming IP for PCI Express* design example? - Why can’t the Agilex® 5 FPGA E‑Series 065B Modular Development Kit be configured using the configuration file generated from the GTS AXI Streaming IP for PCI Express* design example? Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1 with the Agilex® 5 FPGA E‑Series 065B Modular Development Kit (Production) MK‑A5E065AB32AEA development kit preset in the GTS AXI Streaming IP for PCI Express, you may see the following error messages when configuring the development kit using a programming file generated from the PCIe design example using that preset. Error(18939): Unexpected error in JTAG server: Internal error Error(18939): Unexpected error in JTAG server: Invalid OPEN_ID Error(18947): Device not responding Error(18939): Unexpected error in JTAG server: Invalid OPEN_ID Error(209012): Operation failed Resolution To work around this problem, replace the following settings in pcie_ed.qsf file of the GTS AXI Streaming IP for PCI Express Design Example set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO16 set_global_assignment -name USE_CONF_DONE SDM_IO12 set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name USE_INIT_DONE SDM_IO10 set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 74 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 1 set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF with the following settings set_global_assignment -name USE_PWRMGT_SCL SDM_IO14 set_global_assignment -name USE_PWRMGT_SDA SDM_IO11 set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 74 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_125MHZ After that, recompile the design to generate a new programming file. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting QS-21012 novalue ['Interfaces PCIe'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 26.1 ['Agilex™ 5 FPGA E-Series'] ['novalue'] ['novalue'] ['Agilex™ 5 FPGA E-Series 065B Modular Dev Kit']