What is the minimum pulse width for the Hard Processor System cold and warm resets (nPOR, nRST) in Cyclone® V devices? - What is the minimum pulse width for the Hard Processor System cold and warm resets (nPOR, nRST) in Cyclone® V devices? Description The minimum pulse width for the Hard Processor System cold and warm resets (nPOR, nRST) is 6 oscillator 1 (osc1) clock cycles on Cyclone® V devices. The osc1 clock range is 10 - 50 MHz. Resolution This information will be added to the next version of the Cyclone® V handbook. Custom Fields values: ['novalue'] Troubleshooting 2206063873 False ['Reset'] ['FPGA Dev Tools Quartus® Prime Software'] No plan to fix No plan to fix ['Cyclone® V SE FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']