Constraining Source Synchronous Interfaces - Same Course in Simple Chinese: 约束源同步接口 41 Minutes This training will show you how to constrain and analyze single data rate source synchronous interfaces with the Timing Analyzer in the Altera® Quartus® Prime software. You will learn the benefits of source synchronous interfaces as compared to common clock system interfaces. You will be able to write Synopsys* Design Constraints (SDC) to constrain single data rate source synchronous inputs and outputs. You will also learn to use the Timing Analyzer to report and analyze timing for source synchronous inputs and outputs. *Other names and brands may be claimed as the property of others. Course Objectives At course completion, you will be able to: Describe Basic functionality of a source synchronous interface Constrain single data rate source synchronous interfaces with SDC constraints Analyze timing for single data rate source synchronous interfaces with the timing Analyzer Skills Required Completion of timing Analyzer online courses or working knowledge of static timing analysis concepts, creating SDC constraints for clocks and I/Os and timing Analyzer reporting features If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OCSS1000. FPGA_OCSS1000. <p>Constraining Source Synchronous Interfaces</p>