The F-Tile HDMI FPGA IP Design and the F-Tile Architecture and PMA and FEC Direct PHY IP with “HDMI” configuration rule are not of production quality. - The F-Tile HDMI FPGA IP Design and the F-Tile Architecture and PMA and FEC Direct PHY IP with “HDMI” configuration rule are not of production quality. Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 , the F-Tile HDMI FPGA IP Design and the F-Tile PMA/FEC Direct PHY Intel FPGA IP with “HDMI” configuration rule are not completely compliant with the HDMI receiver specifications. Do not use these IP cores in production designs. However, these IP cores can be used for hardware evaluation and simulation. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 15018133097 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']