Why is the DDR3 HMC with multiple MPFE ports hanging in simulation with ModelSim? - Why is the DDR3 HMC with multiple MPFE ports hanging in simulation with ModelSim? Description DDR3 Hard Memory Controller (HMC) designs with two or more MPFE ports enabled may experience a lock-up condition on the Avalon bus when simulating with ModelSim® 10.1b or earlier. This is because the avl_ready signal for each MPFE port will de-assert low and stay low forever, causing the simulation to hang. Resolution This issue has been fixed in Intel® Quartus® Prime Edition Software version 13.0. Custom Fields values: ['novalue'] Troubleshooting 2205797148 False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']