Why is the IRQ_HPD of the DisplayPort Intel® FPGA IP asserted before link training? - Why is the IRQ_HPD of the DisplayPort Intel® FPGA IP asserted before link training? Description The DisplayPort Intel® FPGA IP Sink may assert CR_Lock before link training, and the pseudo-CR_Lock generates pseudo IRQ_HPD before link training. Because CR_Lock and IRQ_HPD are supposed to be valid only during and after link training, the DisplayPort Intel® FPGA IP Source should ignore the pseudo-IRQ_HPD. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 17.1. Custom Fields values: ['novalue'] Troubleshooting 2205907583 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1.1 13.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue'] - 2023-01-07