Why do the transceiver pins of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP not appear in the Chip Planner? - Why do the transceiver pins of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP not appear in the Chip Planner?
Description Due to a problem in the Intel® Quartus® Prime Software version 18.1 and earlier, the transceiver pins of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP do not appear in the Chip Planner. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 19.1.
Custom Fields values:
['novalue']
Troubleshooting
FB: 604184;
False
['Ethernet']
['FPGA Dev Tools Quartus® Prime Software Pro']
19.1
18.1
['Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA']
['novalue']
['novalue']
['novalue'] - 2023-03-27
external_document